SOI structure having a SiGe Layer interposed between the silicon and the insulator

ABSTRACT

A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims benefit of priority under 35 U.S.C. § 119to U.S. provisional application 60/352,260 filed on Jan. 30, 2002, theentire contents of which are incorporated by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to silicon-on-insulator (SOI) waferdevice isolation technology, and more particularly to a method offabricating a modified SOI structure having a buried semiconductorlayer.

[0004] 2. Description of the Related Art

[0005] PN junction isolation between adjacent devices on a bulk siliconsubstrate is used in the manufacture of silicon integrated circuits, butis not suitable for high voltage applications since junction breakdownsoccur at supply voltages of about ± V under appropriate doping level anddimensions. Furthermore, PN junction isolation between the adjacentdevices is not effective in a radioactive environment due to transientphotocurrent caused by gamma rays at the PN junction.

[0006] To overcome the above noted disadvantages of conventional PNjunction isolation techniques, silicon on insulator (SOI) technologieshave been developed. In SOI technologies, a device is completelyencompassed with an insulating material in place of the normal PNjunction. Circuits manufactured on a SOI substrate have advantages inthat the overall chip size is reduced, the fabrication process andresulting structure are simplified compared to circuits manufactured ina bulk silicon substrate, and parasitic capacitances between the devicesand the bulk silicon substrate are reduced to achieve high speedoperation thereof.

[0007] Commonly known techniques for obtaining SOI structures includesilicon-on-sapphire (SOS) which allows heteroepitaxial silicon layer tobe grown on sapphire, separation by implanted oxygen (SIMOX) whichcreates a buried silicon oxide layer by implanting oxygen ions into asilicon substrate and annealing the substrate, and bonding SOI by whichat least one wafer having an insulating layer thereon is bonded toanother wafer.

[0008] Despite the advantages described above, metal-oxide-semiconductor (MOS) field effect transistors (FETs) formed on a SOIwafer have a problem in that a floating body effect occurs because aburied oxide layer isolates the body of the transistor from the siliconsubstrate. When an NMOS transistor is operated, holes generated byimpact ionization are accumulated in the electrically floating body,thereby raising a potential of the body. The increased body potentialreduces the threshold voltage of the device. The increased bodypotential causes an undesirable kink effect in drain current vs. voltagecurves of the NMOS transistor, and induces operation of a parasiticbipolar transistor, thereby leading to an instability of gate controlover source-drain current.

[0009]FIG. 1 is a cross-section of a MOS transistor formed on a SOIwafer having a SiGe layer buried in the body region of the transistorthereon. Referring to FIG. 1, an insulating layer 20 is formed on asubstrate 10. A silicon layer 32, a SiGe layer 34, and a silicon devicelayer 36 are formed in sequence on the insulating layer 20. A gateelectrode 42 is formed on the device layer 36 with a gate insulatinglayer 40 interposed therebetween. A spacer 44 is formed on a sidewall ofthe gate electrode 42. A source region 46 and a drain region 48, both ofwhich are self-aligned to the spacer 44 and doped with impurities, areformed over the device layer 36, the SiGe layer 34, and the siliconlayer 32.

[0010] In the configuration of the transistor of FIG. 1, since thevalence band of the SiGe material exists closer to a Fermi level thanthat of the silicon material, since the SiGe material has a band gapnarrower than the silicon material, a potential barrier for holes islowered at a junction of the SiGe layer 34 and the silicon device layer36. Furthermore, when a drain voltage is applied to the MOS device,electrons cause impact ionization at the drain region 48. The holesgenerated by the impact ionization move to the SiGe layer 34 having alowered potential barrier for holes and then to the source region 46through the SiGe layer 34, thereby suppressing the floating body effect.

[0011] However, since the MOS transistor of FIG. 1 has a partiallydepleted structure, it has relatively low transconductance and lowswitching speed.

SUMMARY OF THE INVENTION

[0012] One object of the present invention is to provide a silicon oninsulator (SOI) structure having a silicon germanium (SiGe) layerinterposed between the silicon and the insulator. The silicon germaniumlayer, due to the narrow band gap characteristics of the SiGe material,suppresses both the floating body effect and the associated kink effectand increases the breakdown voltage (and thereby the drain current) of adrain in a MOS transistor formed on the SOI structure.

[0013] Another object of the present invention is to provide a SOIstructure such that semiconductor devices fabricated on the SOIstructure have improved transconductance and higher switching speeds ascompared to devices on conventional SOI wafers.

[0014] Still another object of the present invention is to providemultiple methods of manufacturing the SOI structure of the presentinvention having a SiGe layer interposed between the silicon layer andthe insulator.

[0015] These and other objects of the present invention are achieved bymethods which fabricate a novel semiconductor structure in which thesemiconductor structure includes an insulator configured to provideelectrical isolation between devices formed in the semiconductorstructure, a silicon germanium layer in direct contact with theinsulator, and a silicon layer in contact with the silicon germaniumlayer.

[0016] In one method of manufacturing the SOI structure of the presentinvention, a first SiGe layer, a silicon layer, and a second SiGe layerare epitaxially grown in sequence over a first substrate, and then aninsulating layer is formed on the second SiGe layer. Then, impurity ionsare implanted into a predetermined location of the first substrateunderlying the first SiGe layer to form an impurity implantation region.A second substrate is bonded to the insulating layer on the firstsubstrate. After the first substrate is separated along the impurityimplantation region and removed, the first SiGe layer remaining on thesurface of the separated region is removed so that the surface of thesilicon layer may be exposed, thereby forming the SOI structure of thepresent invention.

[0017] In one embodiment of this method, the first substrate is formedof silicon, and the impurity ions implanted in the first substrate arehydrogen ions, thus facilitating separation of the first substrate fromthe SiGe layers. The first SiGe layer is formed to a thickness of 10-30Å, and the projected range of the impurity ions implanted duringimpurity ion implantation is 50-100 Å below the first SiGe layer. Afterremoval of the remaining first SiGe layer, the second substrate may beannealed in a hydrogen atmosphere in order to make the surface thereofsmooth.

[0018] In another method of manufacturing the SOI structure of thepresent invention, a SiGe layer and a silicon layer are epitaxiallygrown in sequence on a substrate, and then an insulating layer is formedon the silicon layer. Impurity ions are implanted into a predeterminedlocation of the substrate underlying the SiGe layer to form an impurityimplantation region, and then the substrate is annealed. Subsequently,the substrate between the impurity implantation region and the SiGelayer is thermally oxidized, and the insulating layer formed on thetopmost surface of the substrate is removed, thereby forming the SOIstructure of the present invention.

[0019] In another method of manufacturing the SOI structure of thepresent invention, a porous silicon layer is formed on a firstsubstrate, and then a silicon layer and a SiGe layer are epitaxiallygrown in sequence on the porous silicon layer. Then, an insulating layeris formed on the SiGe layer, and a second substrate is bonded to theinsulating layer on the first substrate. Subsequently, after the bondedfirst and second substrates are annealed and the first substrate. isseparated along the porous silicon layer and removed, the porous siliconlayer remaining on the silicon layer is removed, thereby forming the SOTstructure of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above objects and advantages of the present invention willbecome more apparent by describing in detail preferred embodimentsthereof with reference to the attached drawings in which:

[0021]FIG. 1 is a cross-section of a metal-oxide-semiconductor (MOS)transistor formed on a conventional silicon-on-insulator (SOI) waferhaving a silicon germanium (SiGe) layer interposed on top the siliconlayer of the SOI structure.

[0022]FIG. 2A is a cross-section of a MOS transistor formed on a SOIstructure of the present invention having a silicon germanium (SiGe)layer interposed between the silicon layer and the insulator.

[0023]FIG. 2B is a replica of a cross-sectional transmission electronmicrograph showing one example of the SOI structure of the presentinvention having a SiGe layer in lower contact with a SiO₂ layer forisolation and in upper contact with an epitaxial Si layer;

[0024]FIG. 3 is a schematic energy band diagram of the materials takenalong line A-A′ of FIG. 2;

[0025]FIG. 4 is a schematic energy band diagram of the materials takenalong line B-B′ of FIG. 2;

[0026]FIG. 5 is a graph in which drain current-drain voltage curves of aMOS transistor formed on the SOI structure of the present invention arecompared with those of the MOS transistor formed on a conventional SOIwafer;

[0027]FIG. 6 is a graph in which drain current-gate voltage curves of aMOS transistor formed on the SOI structure of the present invention arecompared with those of the MOS transistor of FIG. 1 formed on aconventional SOI wafer;

[0028] FIGS. 7-12 are cross-sectional views showing a process forfabricating the SOI structure of the present invention;

[0029] FIGS. 13-18 are cross-sectional views showing another process forfabricating the SOI structure of the present invention;

[0030] FIGS. 19-24 are cross-sectional views showing another process forfabricating the SOI structure of the present invention;

[0031] FIGS. 25-30 are cross-sectional views showing another process forfabricating the SOI structure of the present invention;

[0032]FIG. 31 A is a graph depicting a secondary ion mass spectrometer(SIMS) profile of atomic Ge concentration as a function of Ge layerthickness;

[0033]FIGS. 31B and 31 C are graphs depicting, respectively, thesolubility of hydrogen in an alloy of SiGe and the solubility ofhydrogen at a SiGe interface with silicon;

[0034]FIGS. 32 and 33 are graphs depicting atomic concentration profilesfor two different hydrogen implants;

[0035]FIG. 34 is graph depicting a SIMS profile across multiple SiGe/Siepitaxial structures;

[0036]FIG. 35 is a depiction of a cross-sectional transmission electronmicrograph of a SiGe/Si epitaxial structure similar to that depicted inFIG. 35.

DETAILED DESCRIPTION OF THE INVENTION

[0037] This invention may be embodied in many different forms and shouldnot be construed as being limited to the embodiments set forth herein.Rather, these embodiments are provided so that this disclosure will bethorough and complete, and will fully convey the concept of theinvention to those skilled in the art. In the drawings, the thickness oflayers and regions are exaggerated for clarity, and the same referencenumerals appearing in different drawings represent the same element. Itwill also be understood that when a layer is referred to as being “on”another layer or substrate, it can be directly on the other layer orsubstrate, or intervening layers may also be present.

[0038] In the present invention, a silicon germanium (SiGe) layer,having a narrow band gap in order to suppress a floating body effect, isburied in a body region (i.e., an active region of a semiconductordevice) and is in contact with an insulator. This structure serves toisolate the body region of one device from a body region of anotherdevice. Embodiments of the buried SiGe layer on insulator andembodiments of a manufacturing method thereof are described below.

[0039] Referring to FIG. 2A, FIG. 2A depicts an insulating layer 110 ona substrate 100, and depicts a SiGe layer 122 and a device layer 124sequentially located on the insulating layer 110. A gate electrode 142contacts the device layer 124, between which a gate insulating layer 140is interposed. A spacer 144 can be formed, according to the presentinvention, on a sidewall of the gate electrode 142. FIG. 2A depicts asource region 146 and a drain region 148, both of which are self-alignedto the spacer 144 and doped with impurities. The source region 146 andthe drain region 148 are located in the device layer 124 and the SiGelayer 122. The structural difference from the MOS transistor of FIG. 1is that, according to the present invention, the SiGe layer 122 is incontact with the insulating layer 110 and not formed on top the siliconof the SOI structure, as shown in FIG. 1.

[0040]FIG. 2B is a replica of a cross-sectional transmission electronmicrograph showing one example of a fabricated SiGe buried layer of thepresent invention. In the depicted structure, the SiGe buried layer(34.9 nm thick) is in direct contact with a lower SiO₂ layer (230 nmthick) providing electrical isolation and in contact with an upperepitaxial Si layer (143.6 nm thick).

[0041] Suppression of the floating body effect on the SOI structure ofthe present invention will now be described with references to FIGS.3-4. FIGS. 3 and 4 are energy band diagrams of the SiGe layer 122 takenalong lines A-A′ and B-B′ of FIG. 2A, respectively. The floating bodyeffect is closely associated with holes accumulated in the lower portionof a body region of the SOI structure, which is electrically floated bythe insulating layer 110, and significantly affects the operation of anNMOS device. If the MOS device of FIG. 2A is an NMOS transistor, highconcentration of n-type of impurities are implanted to form the sourceregion 146 and the drain region 148. A channel is formed between thesource and drain regions 146 and 148 near the surface of the siliconlayer, which is the device layer 124. If a positive drain voltage isapplied to the drain region 148 in order to operate the NMOS transistor,movement of electrons through the channel causes impact ionization,thereby generating a large number of holes. The generated holes areaccumulated in the body below the channel since the body on the SOIstructure is not grounded. However, the holes easily move to the sourceregion 146 through the SiGe layer 122.

[0042] Thus, in a preferred embodiment of the present invention, asemiconductor structure includes an insulator configured to provideelectrical isolation between devices formed in the semiconductorstructure, a silicon germanium layer in direct contact with theinsulator, and a silicon layer in contact with the silicon germaniumlayer. The silicon layer, due to the respective band gaps of Si and Ge,has a higher band gap than the silicon germanium layer. In one aspect ofthe present invention, the silicon germanium layer is configured toreceive minority carriers from the silicon layer to minimize chargeaccumulation in the silicon layer. In another aspect of the presentinvention, the insulator is an insulating layer formed on asemiconductor substrate. According to the invention, the insulatinglayer can be SiO₂, and the semiconductor can be a silicon wafer. Theinsulator can be, according to the invention, one of a glass, quartz, orsapphire substrate. In another aspect of the present invention, thesilicon germanium layer has a germanium concentration of 5 to 30%. In apreferred embodiment, the germanium concentration ranges from 10-25%.

[0043] In another aspect of the present invention, the silicon germaniumlayer is an epitaxial silicon germanium layer grown initially on aseparate substrate. The silicon layer can be, according to theinvention, an epitaxial silicon layer grown on the epitaxial silicongermanium layer. The silicon germanium layer has a thickness rangingfrom 20 to 50 nm. In a preferred embodiment, the silicon layer has athickness ranging from 100 to 200 nm.

[0044] In another aspect of the present invention, the semiconductorstructure of the present invention includes a drain, a source, and agate insulator formed above the silicon layer, as shown in FIG. 2A, andconfigured to control an active region between the source and the drain.In this aspect, the silicon germanium layer is configured to receiveminority carriers from the silicon layer to thereby minimize chargeaccumulation in the silicon layer, and the silicon germanium layer isconfigured to conduct the minority carriers to the drain.

[0045] Referring to FIG. 3, which is an energy band diagram of ajunction of silicon layer 124 and SiGe layer 122 in the body regionbelow the channel between the source and drain regions 146 and 148, apotential energy Ec of the conduction band of SiGe layer 122 is lowerthan that of the silicon layer 124. A potential energy Ev of the valenceband thereof is higher than that of the silicon layer 124. Thus, theenergy gap or band gap of SiGe layer 122 is about 0.97 eV, which isnarrower than 1.08 eV of the silicon layer 124. That is, the SiGe layer122 exhibits narrow band gap characteristics. In particular, since thepotential energy Ev of balance band of SiGe layer 122 increases toward aFermi level, a potential barrier for holes at the junction betweenlayers 122 and 124 is lowered, thereby preventing accumulation of theholes in the body region and allowing movement of the holes to the SiGelayer 122.

[0046] Referring to FIG. 4, which is an energy band diagram of ajunction between SiGe layer 122 and source region 146, a potentialenergy at the source region 146 in which high concentration of n-type ofimpurities are implanted is higher than that at the body region in whichhigh concentration of p-type of impurities are implanted. Thus, apotential barrier for holes in the SiGe layer 122 within the sourceregion 146 is lowered so that holes moved to the SiGe layer 122 throughthe body region can further be moved to SiGe layer 122 within sourceregion 146, thereby suppressing the floating body effect which is onedisadvantage of a conventional SOI wafer.

[0047]FIG. 5 is a graph in which drain current-drain voltage(I_(d)-V_(d)) curves of a MOS transistor formed on the SOI structure ofthe present invention are compared with those of a MOS transistor formedon a typical SOI (silicon/silicon oxide/silicon) wafer having no SiGelayer. As shown in FIG. 5 on a logarithmic scale, devices formed onconventional SOI wafer show abrupt increases in drain current I_(d) atspecific drain voltages V_(d), thereby exhibiting a kink effect such asshown at a voltage of 1.05 V at a gate voltage Vg of 1V for the lowerset of curves. Devices formed in the SOI structure of the presentinvention exhibit no kink effect at the earlier drain voltages, andconsequently show higher drain currents and higher drain breakdownvoltages.

[0048]FIG. 6 is a graph in which drain current-gate voltage(I_(d)-V_(g)) curves of an MOS transistor formed in the SOI structure ofthe present invention are compared with those of the MOS transistor ofFIG. 1 formed on the conventional wafer. As is evident from FIG. 6, theMOS transistor on the SOI structure of the present invention has asubthreshold slope S significantly larger than that on the transistorformed in the conventional SOI wafer. The larger subthreshold slope Sincreases transconductance and switching speed of MOS transistorfabricated in the SOI structure of the present invention, such as forexample a MOS transistor.

[0049] Methods of manufacturing a SOI structure having a SiGe layeraccording to embodiments of the present invention will now be described.

[0050] First Embodiment

[0051] FIGS. 7-12 are cross-sectional views showing a process forfabricating the SOI structure of the present invention. Referring toFIG. 7, a first SiGe layer 126 is epitaxially grown over a firstsubstrate 140. The first substrate 140 is a monocrystalline siliconsubstrate used as a seed of the epitaxial growth. After loading thesilicon substrate 140, having a purified surface, into a chemical vapordeposition (CVD) apparatus heated to a predetermined temperature, suchas for example, 700° C., a reactive gas including silicon (e.g. Si₂H₆,SiH₄, SiCl₄ etc) is supplied with a reactive gas including germanium(e.g. GeH₄, Ge₂H₆, etc.) to grow the first SiGe layer 126 over thesilicon substrate 140. When the first SiGe layer 126 is grown to apredetermined thickness, for example, 10-50 Å, preferably, 20 Å, the Gereactive gas ceases to be supplied, and continuously, a silicon layer,which will be a device layer 124, is epitaxially grown in situ to athickness of several hundreds to thousands of Angstroms, for example,between 500 and 1800 Å in this embodiment. Then, the Ge reactive issupplied again to epitaxially grow a second SiGe layer 122 to athickness of several hundreds to thousands of angstroms, for example,about 300 Å.

[0052] Referring to FIG. 8, a silicon oxide layer is formed, on theepitaxially grown second SiGe layer 122, as an insulating layer 132 to athickness of several hundreds to thousands of Angstroms, for example,about 1,000 Å. The insulating layer 132 may be deposited using variouschemical or physical deposition techniques or formed by thermaloxidation techniques, all of which are known to those skilled in theart.

[0053] Referring to FIG. 9, hydrogen ions are implanted into the top ofthe first substrate 140 to form a hydrogen implantation region 128.Techniques for implanting hydrogen ions (and separating a substratealong the hydrogen implantation region) are described in U.S. Pat. Nos.5,882,987 and 6,033,974, the entire contents of which are incorporatedherein by reference. More specifically in this example, an ionimplantation energy is controlled such that the projected range R_(p) ofthe implanted ions reaches a depth of 50-100 Å beneath the first SiGelayer 126, and an implantation dose is in the range of 3.5×10¹⁵ to3.5×10¹⁷ atoms/cm². Setting the projected range R_(p) in this wayfacilitates separation caused by a mismatch between the siliconsubstrate 140 and the first SiGe layer 126.

[0054]FIG. 31A depicts a secondary ion mass spectrometer (SIMS) profileof atomic Ge concentration as a function of Ge layer thickness, showingthat Ge concentration increased with Ge layer thickness although the gasconcentration of GeH₄ was fixed. FIG. 31 B depicts the solubility of H₂in SiGe layer is two times higher than in Si layer. FIG. 31 C depictsconcentration of hydrogen accumulated in SiGe layer increased with Geconcentration. As can be seen from FIG. 31A, 31B, and 31C, the amount ofhydrogen accumulated at the interface is directly related to the Geconcentration. The propagation of a crack (i.e., cleavage) along thehydrogen accumulated interface is caused by the mismatch between theSiGe layer and the Si.

[0055] The resultant surface roughness following cleavage is a functionof the hydrogen implant dose and the SiGe layer thickness. The effect ofhydrogen accumulation at an interface between SiGe and Si is shown inFIGS. 32 and 33 for two different hydrogen implants into an epitaxialSiGe/Si structure having doses of 2×10¹⁶ atoms/cm² and 6×10¹⁵ atoms/cm²,respectively The absolute concentrations of Ge and hydrogen dose are notcritical and the values given here are shown only to illustrate theeffect of hydrogen accumulation at SiGe interfaces and are not given tounduly limit the present invention. The accumulation of hydrogen at theinterface is driven by strain at the interface arising from thedifference in lattice constants between the Si and the epitaxial SiGelayer. FIG. 34 is a SIMS profile across a SiGe/Si epitaxial structureshowing the same effect of hydrogen accumulation for hydrogenaccumulations at the interface approaching the maximum soluble limit ofhydrogen in the SiGe alloy of 20% Ge. As before, hydrogen accumulatespreferentially at the interfaces. FIG. 35 is a depiction of across-sectional transmission electron micrograph of a SiGe/Si epitaxialstructure similar to that epitaxial SiGe/Si structure depicted in FIG.34. Note the contrast in the electron micrograph about the first SiGelayer with a thickness of 29 nm. The accumulation of the hydrogen at theSiGe interface disrupts the lattice of the SiGe/Si epitaxial structurenear the interface such that a cavity is created as the solid isconverted to a hydride. For low dose rate implants, the resultant cavitydimension can be small, resulting in a cleavage having less than a 50 Åsurface roughness for a dose rate of 5×101¹⁶ atoms/cm², after an annealat 400° C. for 30 min, for a SiGe layer with a 20% concentration.

[0056] Cleavage along the disrupted interface provides a methodaccording to the present invention for separating the SiGe/Si epitaxialstructures at one of the internal interfaces between the SiGe and theSi.

[0057] Referring now to FIG. 10, the surface of the insulating layer 132formed on the topmost surface of the first substrate 140 is cleaned, andthen a second substrate 100 is bonded to the insulating layer 132. Thebonding process is performed by compressing both substrates 100 and 140at room temperature. Then, the substrate 100 is annealed at 400-600° C.to form a hybrid phase at the hydrogen implantation region 128 therebyfacilitating a subsequent cleaving or separation. While the secondsubstrate 100 has been shown in this embodiment without an insulatinglayer, the second substrate 100 having an insulating layer such assilicon oxide thereon may be used. Alternatively, the second substratecan itself be an insulating substrate such as for example glass, quartz,or sapphire.

[0058] Referring to FIG. 11, the substrate 130 is separated along thehydrogen implantation region 128 and removed. To make the bondingbetween each layer on the second substrate 100 stronger, the substrate100 is annealed at above 1,100° C. in a nitrogen ambient for a time inthe range of 1 to 2 hours.

[0059] Referring to FIG. 12, the first SiGe layer 126 remaining on thedevice layer 124 is selectively removed using a chemical etch, therebycompleting the manufacture of the SOI structure of the present inventionhaving the second SiGe layer 122 directly in contact with the insulatinglayer 132. In order to make the exposed surface of the device layer 124smooth, the wafers may be transferred to an epitaxial reaction chamberto perform hydrogen annealing in a hydrogen atmosphere above 1150° C.for >5 min.

[0060] Second Embodiment

[0061] FIGS. 13-18 are cross-sectional views showing a process forfabricating the SOI structure of the present invention. Unlike the firstembodiment, the second embodiment isolates the buried SiGe layer byseparation implanted oxygen (SIMOX). The SIMOX process implants oxygenions into a silicon substrate upon which thermal oxidation forms anintermediate insulating layer. The SIMOX techniques are described inSadao Nakashima “High-quality Low-dose SIMOX Wafers”, IEICE TRANSELECTRON, VOL. E80C, NO.3, pp364-369, March 1997, the entire contents ofwhich are incorporated herein by reference. Further, SIMOX techniquesare described in U.S. Pat. No. 6,486,037, the entire contents of whichare incorporated herein by reference.

[0062] Referring to FIG. 13, a SiGe layer 126 is epitaxially grown overa substrate 140. The substrate 140 is a monocrystalline siliconsubstrate used as a seed of this epitaxial growth. After loading thesilicon substrate 140 having a purified surface into a chemical vapordeposition (CVD) apparatus heated to a predetermined temperature, forexample, 700° C., a reactive gas including silicon, as discussedpreviously, is supplied with a reactive gas including germanium, asdiscussed previously) to grow the SiGe layer 126 over the siliconsubstrate 140. When the SiGe layer 126 is grown to a predeterminedthickness, for example, 200-400 Å, preferably, 300 Å, the reactive gasincluding Ge ceases to be supplied, and continuously, a silicon layer,which will be a device layer 124, is epitaxially grown in situ to athickness of several hundreds to thousands of angstroms, for example,about 2,400 Å in this embodiment.

[0063] Referring to FIG. 14, a silicon oxide layer is formed on theepitaxially grown device layer 124 as an insulating layer 132 to athickness of several hundreds to thousands of angstroms, for example,about 1,000 Å. The insulating layer 132 may be deposited using thevarious deposition and thermal oxidation techniques previously noted.

[0064] Referring to FIG. 15, oxygen ions are implanted into the top ofthe substrate 140 to form an oxygen implantation region 134. Morespecifically, an ion implantation energy is controlled such that theprojected range R_(p) of the implanted ions is about 4,200 Å from thesurface of the insulating layer 132, i.e., about 500 Å from below theSiGe layer 126. In this embodiment, ion implantation is performed at animplantation energy of 180 KeV and at an implantation dose of 3.0×10¹⁵to 4.5×10¹⁷ atoms/cm².

[0065] Referring to FIG. 16, a high temperature anneal is performed tooxidize the oxygen implantation region 134 and form an insulating layer136 formed of silicon oxide. The high temperature annealing is performedat about 1,300° C. for several hours, for example, about 4 hours, in anargon atmosphere containing less than 1% oxygen.

[0066] Referring to FIG. 17, a high temperature thermal oxidation isperformed at above 1,300° C. so that the silicon substrate 140 betweenthe oxygen implantation region 134 and the SiGe layer 126 is completelyoxidized. Thus, the top surface of the insulating layer 136 is incontact with the SiGe layer 126. The high temperature thermal oxidationis performed in an argon atmosphere containing oxygen greater than 50%.Here, the thickness of the insulating layer 136 is approximately 1,000Å.

[0067] Referring to FIG. 18, the insulating layer 132 formed on thetopmost surface of the substrate 140 is selectively removed using wetchemicals to complete the manufacture of the SOI structure of thepresent invention.

[0068] Third Embodiment

[0069] FIGS. 19-24 are cross-sectional views showing a process forfabricating the SOI structure of the present invention. Like the firstembodiment, the third embodiment involves implanting hydrogen ions toform a cleavage region. The difference is that a single SiGe layer isformed.

[0070] Referring to FIG. 19, a silicon layer 124 is epitaxially grownover a first substrate 140 formed of silicon. The first substrate 140 isa monocrystalline silicon substrate used as a seed of this epitaxialgrowth. The silicon layer 124 is epitaxially grown to a thickness ofseveral hundreds to thousands of angstroms, for example, 500 and 1800 Åin this embodiment. Then, the reactive gas including germanium issupplied again to epitaxially grow a SiGe layer 126 to a thickness ofseveral hundreds to thousands of angstroms, for example, about 300 Å.

[0071] Referring to FIG. 20, a silicon oxide layer is formed on theepitaxially grown SiGe layer 126 as an insulating layer 132 to athickness of several hundreds to thousands of angstroms, for example,about 1,000 Å. The insulating layer 132 may be deposited using variouschemical or physical deposition techniques or formed by thermaloxidation.

[0072] Referring to FIG. 21, hydrogen ions are implanted into the top ofthe first substrate 140 to form a hydrogen implantation region 128. Morespecifically, an ion implantation energy is controlled such that theprojected range R_(p) of the implanted ions reaches a depth of severaltens to hundreds of Angstroms beneath the silicon layer 124. The ionimplantation is performed at an implantation energy of 95 KeV and at animplantation dose of 3.5×10¹⁶ to 3.5×10¹⁷ atoms/cm².

[0073] Referring to FIG. 22, the surface of the insulating layer 132formed on the topmost surface of the first substrate 140 is cleaned, andthen a second substrate 100 is bonded to the insulating layer 132. Thebonding process is performed by compressing both substrates 100 and 140at room temperature. Then, the substrate 100 is annealed at 400-600° C.to form a hybrid phase at the hydrogen implantation region 128 therebyfacilitating a subsequent cleaving or separation. While only the secondsubstrate 100 has been used in this embodiment, a second substratehaving an insulating layer such as silicon oxide may be used, or aspreviously discussed, the second substrate itself can be insulating.

[0074] Referring to FIG. 23, the first substrate 140 is separated alongthe hydrogen implantation region 128 and removed. Techniques forimplanting hydrogen ions to separate a substrate along the hydrogenimplantation region are described in U.S. Pat. Nos. 5,882,987 and6,033,974 described above. To make the bonding between each layer on thesecond substrate 100 stronger, the substrate 100 is annealed at above1,100° C. for a time in the range of 1 to 2 hours.

[0075] Referring to FIG. 24, a part of the first substrate 140 remainingon the device layer 124 is selectively removed using a chemical etch orby chemical mechanical polishing (CMP) to expose the device layer 124,thereby completing the manufacture of a SOI structure having the SiGelayer 126 formed directly on the insulating layer 132. In order to makethe exposed surface of the device layer 124 smooth, the substrate 100may be transferred to an epitaxial reaction chamber to perform hydrogenannealing in a hydrogen atmosphere.

[0076] Fourth Embodiment

[0077] FIGS. 25-30 are cross-sectional views showing a process forfabricating a bonded SOI structure according to a fourth embodiment ofthe present invention. Referring to FIG. 25, a porous silicon layer 138is formed on a first substrate 140 made of silicon. The first substrate140 is a single crystalline silicon substrate, and anodization isperformed on a surface of the single crystalline silicon substrate 140using an HF solution to form the porous silicon layer 138. Anodizationtechniques for forming a porous silicon layer are described in U.S. Pat.No. 5,876,497, the entire contents of which are incorporated herein byreference. In a preferred embodiment of the present invention,anodization is performed in 40% HF+C₂H₅OH (2:1) and with current densityof 7 mA/cm² to form the porous silicon layer 138 having a thickness of12 μm.

[0078] Referring to FIG. 26, a silicon layer 124 is epitaxially grown onthe porous silicon layer 138 to a predetermined thickness, for example,several hundreds to thousands of Angstroms, 500 and 1800 Å in thisembodiment. Then, the reactive gas including germanium is supplied toepitaxially grow a SiGe layer 126 to a thickness of several hundreds tothousands of angstroms, for example, about 300 Å.

[0079] Referring to FIG. 27, a silicon oxide layer is formed on the SiGelayer 126 as an insulating layer 132 to a thickness of several hundredsto thousands of angstroms, for example, about 1,000 Å. The insulatinglayer 132 may be deposited using various chemical or physical depositiontechniques or formed by thermal oxidation.

[0080] Referring to FIG. 28, the surface of the insulating layer 132formed on the topmost surface of the first substrate 140 is cleaned, andthen a second substrate 100 is bonded to the insulating layer 132,followed by high temperature annealing. The bonding process is performedby compressing both substrates 100 and 140 at room temperature. Then,the second substrate 100 is annealed at about 1,180° C. While the secondsubstrate 100 has been shown in this embodiment without an insulatinglayer, the second substrate 100 having an insulating layer such assilicon oxide thereon may be used, or as previously discussed the secondsubstrate itself can be insulating.

[0081] Referring to FIG. 29, the first substrate 140 is separated alongthe porous silicon layer 138 and removed.

[0082] Referring to FIG. 30, a part of the porous silicon layer 138remaining on a device layer 124 as shown in FIG. 29 is selectivelyremoved using a chemical etch or by chemical mechanical polishing (CMP)to expose the device layer 124, thereby completing the manufacture of aSOI structure having the SiGe layer 126 formed directly on theinsulating layer 132.

[0083] A mixture of 40% HF, 70% HNO₃, and 98% CH₃COOH is used as anetching solution for removing the porous silicon layer 138. To make theexposed surface of the device layer 124 smooth and to promote boronout-diffusion, the substrate 100 may be transferred to an epitaxialreaction chamber to perform hydrogen annealing in a hydrogen atmosphereat a temperature of 1,000° C. at a pressure of 760 Torr.

[0084] As described above, according to the present invention, a SiGelayer interposed between a silicon layer and an insulator of asilicon-on-insulator structure and having a narrow band gap is formed ina body and a source/drain region of a semiconductor device, the SiGeburied layer suppresses the floating body effect and the kink effect andincreases the breakdown voltage of a drain of a device formed with theburied SiGe layer, thus improving transconductance and switching speedof a MOS transistor formed thereon. Furthermore, the methods ofmanufacturing a bonding SOI structure according to this invention arereadily implemented and facilitate the control of thickness uniformityof the epitaxial SiGe and Si layers.

[0085] Numerous modifications and variations of the present inventionare possible in light of the above teachings. It is therefore to beunderstood that within the scope of the appended claims, the inventionmay be practiced otherwise than as specifically described herein.

1. A semiconductor structure comprising: an insulator configured toprovide electrical isolation; a silicon germanium layer in directcontact with said insulator; and a silicon layer in contact with saidsilicon germanium layer, said silicon layer having a higher band gapthan said silicon germanium layer.
 2. The structure of claim 1, whereinsaid silicon germanium layer is configured to receive minority carriersfrom the silicon layer to minimize charge accumulation in the siliconlayer.
 3. The structure of claim 1, further comprising: a semiconductorsubstrate; and said insulator comprising an insulating layer formed onsaid semiconductor substrate.
 4. The structure of claim 3, wherein theinsulating layer comprises SiO₂.
 5. The structure of claim 3, whereinthe semiconductor comprises a silicon wafer.
 6. The structure of claim1, wherein the insulator comprises at least one of a glass substrate, aquartz substrate, and a sapphire substrate.
 7. The structure of claim 1,wherein the silicon germanium layer has a germanium concentration of 5to 30%.
 8. The structure of claim 7, wherein the germanium concentrationranges from 10-25%.
 9. The structure of claim 1, wherein the silicongermanium layer comprises an epitaxial silicon germanium layer growninitially on a separate substrate.
 10. The structure of claim 9, whereinthe silicon layer comprises an epitaxial silicon layer grown on saidepitaxial silicon germanium layer.
 11. The structure of claim 1, whereinthe silicon germanium layer has a thickness ranging from 20 to 50 nm.12. The structure of claim 1, wherein the silicon layer has a thicknessranging from 100 to 200 nm.
 13. The structure of claim 1, furthercomprising: a drain formed in at least the silicon layer; a sourceformed in at least the silicon layer; a gate insulator formed above saidsilicon layer; and a gate electrode formed above said gate insulator,said gate electrode configured to control an active region between saidsource and said drain.
 14. The structure of claim 13, wherein thesilicon germanium layer is configured to receive minority carriers fromthe silicon layer to minimize charge accumulation in the silicon layer.15. The structure of claim 13, wherein the silicon germanium layer isconfigured to conduct said minority carriers to said drain.
 16. A methodof manufacturing a silicon on insulator SOI wafer having a silicongermanium SiGe layer in contact with said insulator, comprising:epitaxially growing a first SiGe layer, a silicon layer, and a secondSiGe layer in sequence on a first substrate; forming an insulating layeron the second SiGe layer; implanting impurity ions into a predeterminedlocation of the first substrate underlying the first SiGe layer to forman impurity implantation region; bonding a second substrate to theinsulating layer on the first substrate; and separating the firstsubstrate along the impurity implantation region and removing the firstsubstrate.
 17. The method of claim 16, further comprising: removing thefirst SiGe layer remaining on a surface of a separated region of thesecond substrate so that the surface of the silicon layer is exposed.18. The method of claim 17, further comprising: annealing the secondsubstrate in an hydrogen atmosphere after removal of the remaining firstSiGe layer.
 19. The method of claim 16, wherein the epitaxially growingcomprises epitaxially growing on a silicon substrate.
 20. The method ofclaim 16, wherein the epitaxially growing the first SiGe layercomprises: epitaxially growing the first SiGe layer to a thickness of10-50 Å.
 21. The method of claim 16, wherein the forming an insulatinglayer comprises: forming a silicon oxide layer.
 22. The method of claim16, wherein the implanting impurity ions comprises: implanting hydrogenimpurity ions.
 23. The method of claim 16, wherein the implantingimpurity ions comprises: implanting the impurity ions below the firstSiGe layer.
 24. The method of claim 16, wherein the implanting impurityions comprises: implanting the impurity ions at a depth of 50-100 Åbelow the first SiGe layer.
 25. The method of claim 16, furthercomprising: annealing the second substrate after separation of the firstsubstrate.
 26. The method of claim 16, wherein the annealing comprises:annealing the second substrate at a temperature above 1,100° C. for atime in a range of 1 to 2 hours after separation of the first substrate.27. A method of manufacturing a silicon on insulator (SOI) wafer havinga silicon germanium (SiGe) layer, comprising: epitaxially growing theSiGe layer and a silicon layer in sequence on a substrate; forming aninsulating layer on the silicon layer; implanting impurity ions into apredetermined location of the substrate underlying the SiGe layer toform an impurity implantation region; annealing the substrate; andthermally oxidizing the impurity implantation region to form saidinsulator of said SOI wafer.
 28. The method of claim 27, furthercomprising: removing said insulating layer formed on a topmost surfaceof the substrate.
 29. The method of claim 27, wherein the epitaxiallygrowing comprises: epitaxially growing the SiGe layer on a siliconsubstrate.
 30. The method of claim 27, wherein the epitaxially growingcomprises: epitaxially growing the SiGe layer to a thickness of 200-300Å.
 31. The method of claim 27, wherein the implanting comprises:implanting at least oxygen impurity ions.
 32. The method of claim 27,wherein the forming an insulating layer comprises: forming a siliconoxide layer.
 33. The method of claim 27, wherein the implanting impurityions comprises: implanting the impurity ions below the SiGe layer. 34.The method of claim 33, wherein the implanting impurity ions comprises:implanting the impurity ions implanted at a depth 400-600 Å from belowthe SiGe layer.
 35. The method of claim 27, wherein the annealingcomprises: annealing at a temperature above 1,300° C. in an argonatmosphere containing less than 1% oxygen.
 36. The method of claim 27,wherein the annealing comprises: oxidizing at a temperature above 1,300°C. in an argon atmosphere containing greater than 50% oxygen.
 37. Amethod of manufacturing a silicon on insulator (SOI) wafer having asilicon germanium (SiGe) layer thereon, comprising: forming a poroussilicon layer on a first substrate; epitaxially growing a silicon layerand the SiGe layer in sequence on the porous silicon layer; forming aninsulating layer on the SiGe layer; bonding a second substrate to theinsulating layer on the first substrate to form a bonded first andsecond substrate; annealing the bonded first and second substrate;separating the first substrate from the bonded first and secondsubstrate along the porous silicon layer and removing the firstsubstrate; and removing remnants of the porous silicon layer.
 38. Themethod of claim 37, wherein the forming a porous silicon layercomprises: performing an anodization of the first substrate.
 39. Themethod of claim 37, wherein the forming an insulating layer comprises:forming a silicon oxide layer.
 40. The method of claim 37, wherein theremoving remnants comprises: etching the remnants a mixture of 40% HF,70% HNO₃, and 98% CH₃COOH.
 41. The method of claim 37, furthercomprising: annealing the second substrate in a hydrogen atmosphereafter removal of the porous silicon layer.